SIC417CD-T1-E3【PDF 12/19 页】IC REG DL BCK/LINEAR SYNC 32MLPQ

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录46

8页 9页 10页 11页 [12页]13页 14页 15页 16页

www.vishay.com

Document Number: 69062

S10-1367-Rev. D, 14-Jun-10

Vishay Siliconix

SiC417

To avoid unwanted switch-over, the minimum difference

between the voltages for V

OUT

and V

LDO

should be

?500 mV.

It is not recommended to use the switch-over feature for an

output voltage less than 3 V since this does not provide

sufficient voltage for the gate-source drive to the internal

p-channel switch-over MOSFET.

Switch-Over MOSFET Parasitic Diodes

The switch-over MOSFET contains parasitic diodes that are

inherent to its construction, as shown in figure 11.

There are some important design rules that must be followed

to prevent forward bias of these diodes. The following two

conditions need to be satisfied in order for the parasitic

diodes to stay off.

" V5V e V

LDO

" V5V e V

OUT

If either V

LDO

or V

OUT

is higher than V5V, then the respective

diode will turn on and the SiC417 operating current will flow

through this diode. This has the potential of damaging the

device.

ENL Pin and V

UVLO

The ENL pin also acts as the switcher under-voltage lockout

for the V

supply. The V

UVLO voltage is programmable

via a resistor divider at the V

, ENL and A

GND

pins.

ENL is the enable/disable signal for the LDO. In order to

implement the V

UVLO there is also a timing requirement

that needs to be satisfied.

If the ENL pin transitions low within 2 switching cycles and is

< 1 V, then the LDO will turn off but the switcher remains on.

If ENL goes below the V

UVLO threshold and stays above

1 V, then the switcher will turn off but the LDO remains on.

The V

UVLO function has a typical threshold of 2.6 V on the

rising edge. The falling edge threshold is 2.4 V.

Note that it is possible to operate the switcher with the LDO

disabled, but the ENL pin must be below the logic low

threshold (0.4 V maximum).

ENL Logic Control of PWM Operation

When the ENL input is driven above 2.6 V, it is impossible to

determine if the LDO output is going to be used to power the

device or not. In self-powered operation where the LDO will

power the device, it is necessary during the LDO start-up to

hold the PWM switching off until the LDO has reached 90 %

of the final value. This is to prevent overloading the

current-limited LDO output during the LDO start-up.

However, if the switcher was previously operating (with EN/

PSV high but ENL at ground, and V5V supplied externally),

then it is undesirable to shut down the switcher.

To prevent this, when the ENL input is taken above 2.6 V

(above the V

UVLO threshold), the internal logic checks the

GOOD

signal. If P

GOOD

is high, then the switcher is already

running and the LDO will run through the start-up cycle

without affecting the switcher. If P

GOOD

is low, then the LDO

will not allow any PWM switching until the LDO output has

reached 90 % of it's final value.

On-Chip LDO Bias the SiC417

The following steps must be followed when using the onchip

LDO to bias the device.

" Connect V5V to V

LDO

before enabling the LDO.

" The LDO has an initial current limit of 85 mA at start-up

with 12 V

, therefore, do not connect any external load to

LDO

during start-up.

" When V

LDO

reaches 90 % of its final value, the LDO

current limit increases to 200 mA. At this time the LDO may

be used to supply the required bias current to the device.

" Switching will be held off until V

LDO

reaches regulation.

Attempting to operate in self-powered mode in any other

configuration can cause unpredictable results and may

damage the device.

Design Procedure

When designing a switch mode power supply, the input

voltage range, load current, switching frequency, and

inductor ripple current must be specified.

The maximum input voltage (V

INMAX

) is the highest specified

input voltage. The minimum input voltage (V

INMIN

) is

determined by the lowest input voltage after evaluating the

voltage drops due to connectors, fuses, switches, and PCB

traces.

The following parameters define the design:

" Nominal output voltage (V

OUT

)

" Static or DC output tolerance

" Transient response

" Maximum load current (I

OUT

)

There are two values of load current to evaluate - continuous

load current and peak load current. Continuous load current

relates to thermal stresses which drive the selection of the

inductor and input capacitors. Peak load current determines

instantaneous component stresses and filtering

requirements such as inductor saturation, output capacitors,

and design of the current limit circuit.

The following values are used in this design:

" V

= 12 V ?10 %

" V

OUT

= 1.05 V ?4 %

" f

= 250 kHz

" Load = 10 A maximum

Figure 11 - Switch-over MOSFET Parasitic Diodes

OUT

LDO

V5V

Parastic diode

Switchover

MOSFET

Switchover

control

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式